User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 91 of 909 2019 Ambiq Micro, Inc.
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3.5.3.1.2.11DEVPWREVENTEN Register
Event enable register to control which DEVPWRSTATUS bits are routed to event input of CPU.
OFFSET: 0x00000028
INSTANCE 0 ADDRESS: 0x40021028
This register controls which feature trigger will result in an event to the CPU. It includes all the power on
status for the core domains, as well as the Burst event. If any bits are set, then if the domain is turned on,
it will result in an event to the ARM core.
0 SIMOBUCKEN 0x0 RW
Enables and Selects the SIMO Buck as the supply for the low-voltage power
domain. It takes the initial value from the bit set in Customer INFO space.
EN = 0x1 - Enable the SIMO Buck
DIS = 0x0 - Disable the SIMO Buck
Table 27: DEVPWREVENTEN Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
BURSTEVEN
BURSTFEATUREEVEN
BLEFEATUREEVEN
RSVD
BLELEVEN
PDMEVEN
MSPIEVEN
ADCEVEN
HCPCEVEN
HCPBEVEN
HCPAEVEN
MCUHEVEN
MCULEVEN
Table 28: DEVPWREVENTEN Register Bits
Bit Name Reset RW Description
31 BURSTEVEN 0x0 RW
Control BURST status event
EN = 0x1 - Enable BURST status event
DIS = 0x0 - Disable BURST status event
30
BURSTFEATU-
REEVEN
0x0 RW
Control BURSTFEATURE status event
EN = 0x1 - Enable BURSTFEATURE status event
DIS = 0x0 - Disable BURSTFEATURE status event
29
BLEFEATU-
REEVEN
0x0 RW
Control BLEFEATURE status event
EN = 0x1 - Enable BLEFEATURE status event
DIS = 0x0 - Disable BLEFEATURE status event
28:9 RSVD 0x0 RO
RESERVED.
Table 26: MISC Register Bits
Bit Name Reset RW Description