User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 90 of 909 2019 Ambiq Micro, Inc.
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Table 25: MISC Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
FORCEBLEBUCKACT
MEMVRLPBLE
FORCEMEMVRADC
FORCEMEMVRLPTIMERS
FORCECOREVRLPTIMERS
FORCECOREVRLPPDM
SIMOBUCKEN
Table 26: MISC Register Bits
Bit Name Reset RW Description
31:8 RSVD 0x0 RO
RESERVED.
7
FORCEBLE-
BUCKACT
0x0 RW
Control Bit to enable BLE Buck to be in active state when BLE Buck is
enabled. Default behavior is to be in active only when Burst or BLEH power
on are requested.
6 MEMVRLPBLE 0x0 RW
Control Bit to let Mem VR go to lp mode in deep sleep even when BLEL or
BLEH is powered on given none of the other domains require it.
EN = 0x1 - Mem VR can go to lp mode even when BLE is powered on.
DIS = 0x0 - Mem VR will stay in active mode when BLE is powered on.
5:4
FORCEMEM-
VRADC
0x0 RW
Control Bit to force mem VR to LP or ACT mode in deep sleep when ADC is
powered ON. 0x3 results in picking LP mode.
ACT = 0x2 - In this mode if all the other domains but ADC are powered
down, mem VR will stay in ACT mode.
LP = 0x1 - In this mode if all the other domains but ADC are powered down,
mem VR will stay in LP mode.
DIS = 0x0 - In this mode if all the other domains but ADC are powered
down, mem VR will duty cycle between active and LP modes depending on
ADC sampling.
3
FORCEMEM-
VRLPTIMERS
0x0 RW
Control Bit to force Mem VR to LP mode in deep sleep even when hfrc
based ctimer or stimer is running.
2
FORCECOREV-
RLPTIMERS
0x0 RW
Control Bit to force Core VR to LP mode in deep sleep even when hfrc
based ctimer or stimer is running.
1
FORCECOREV-
RLPPDM
0x0 RW
Control bit to enable the core VR to go into LP mode with HCPA/B/C/MSPI
are powered off but PDM is powered on