User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 89 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
3.5.3.1.2.10MISC Register
Power Optimization Control Bits
OFFSET: 0x00000024
INSTANCE 0 ADDRESS: 0x40021024
This register includes additional debug control bits. This is an internal Ambiq-only register. Customers
should not attempt to change this or else functionality cannot be guaranteed.
Table 23: ADCSTATUS Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
REFBUFPWD
REFKEEPPWD
VBATPWD
VPTATPWD
BGTPWD
ADCPWD
Table 24: ADCSTATUS Register Bits
Bit Name Reset RW Description
31:6 RSVD 0x0 RO
RESERVED.
5 REFBUFPWD 0x1 RO
This bit indicates that the ADC REFBUF is powered down
4 REFKEEPPWD 0x1 RO
This bit indicates that the ADC REFKEEP is powered down
3 VBATPWD 0x1 RO
This bit indicates that the ADC VBAT resistor divider is powered down
2 VPTATPWD 0x1 RO
This bit indicates that the ADC temperature sensor input buffer is powered
down
1BGTPWD 0x1RO
This bit indicates that the ADC Band Gap is powered down
0 ADCPWD 0x1 RO
This bit indicates that the ADC is powered down