User Manual

Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 87 of 909 2019 Ambiq Micro, Inc.

3.5.3.1.2.8SRAMCTRL Register

SRAM Control register

OFFSET: 0x0000001C

INSTANCE 0 ADDRESS: 0x4002101C

This register provides additional fine-tune power management controls for the SRAMs and the SRAM

controller. This includes enabling light sleep for the SRAM and TCM banks, and clock gating for reduced

dynamic power.

Table 20: DEVPWRSTATUS Register Bits

Bit Name Reset RW Description

SYSDEEPS-

LEEP

0x0 RO

This bit is 1 if SYSTEM has been in Deep Sleep. Write '1' to this bit to clear

it.

COREDEEPS-

LEEP

0x0 RO

This bit is 1 if CORE has been in Deep Sleep. Write '1' to this bit to clear it.

29 CORESLEEP 0x0 RO

This bit is 1 if CORE has been in SLEEP State. Write '1' to this bit to clear it.

28:10 RSVD 0x0 RO

This bitfield is reserved for future use.

9BLEH 0x0RO

This bit is 1 if power is supplied to BLEH

8BLEL 0x0RO

This bit is 1 if power is supplied to BLEL

7PWRPDM 0x0RO

This bit is 1 if power is supplied to PDM

6 PWRMSPI 0x0 RO

This bit is 1 if power is supplied to MSPI

5PWRADC 0x0RO

This bit is 1 if power is supplied to ADC

4 HCPC 0x0 RO

This bit is 1 if power is supplied to HCPC domain (IO MASTER4, 5, 6)

3 HCPB 0x0 RO

This bit is 1 if power is supplied to HCPB domain (IO MASTER 0, 1, 2)

2 HCPA 0x0 RO

This bit is 1 if power is supplied to HCPA domain (IO SLAVE, UART0,

UART1, SCARD)

1 MCUH 0x1 RO

This bit is 1 if power is supplied to MCUH

0 MCUL 0x1 RO

This bit is 1 if power is supplied to MCUL