User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 86 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
3.5.3.1.2.7DEVPWRSTATUS Register
Device Power ON Status
OFFSET: 0x00000018
INSTANCE 0 ADDRESS: 0x40021018
This provides the power status for the peripheral devices- BLEL, PDM, PDM, MSPI, SCARD, ADC, UART0
& 1, IOM5 to 0, IOSLAVE and MCUL (DMA and Fabrics) and MCUH (ARM core). The status here should
reflect the enable provided by the DEVPWREN register. There may be a lag time between setting the bits
in DEVPWREN register and DEVPWRSTATUS register, due to the need to cycle the power gate, isolation
and reset seqeunces to the device power domains.
10 SRAM7 0x1 RO
This bit is 1 if power is supplied to SRAM GROUP7
9SRAM6 0x1RO
This bit is 1 if power is supplied to SRAM GROUP6
8SRAM5 0x1RO
This bit is 1 if power is supplied to SRAM GROUP5
7SRAM4 0x1RO
This bit is 1 if power is supplied to SRAM GROUP4
6SRAM3 0x1RO
This bit is 1 if power is supplied to SRAM GROUP3
5SRAM2 0x1RO
This bit is 1 if power is supplied to SRAM GROUP2
4SRAM1 0x1RO
This bit is 1 if power is supplied to SRAM GROUP1
3SRAM0 0x1RO
This bit is 1 if power is supplied to SRAM GROUP0
2DTCM1 0x1RO
This bit is 1 if power is supplied to DTCM GROUP1
1DTCM01 0x1RO
This bit is 1 if power is supplied to DTCM GROUP0_1
0DTCM00 0x1RO
This bit is 1 if power is supplied to DTCM GROUP0_0
Table 19: DEVPWRSTATUS Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
SYSDEEPSLEEP
COREDEEPSLEEP
CORESLEEP
RSVD
BLEH
BLEL
PWRPDM
PWRMSPI
PWRADC
HCPC
HCPB
HCPA
MCUH
MCUL
Table 18: MEMPWRSTATUS Register Bits
Bit Name Reset RW Description