User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 85 of 909 2019 Ambiq Micro, Inc.
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3.5.3.1.2.6MEMPWRSTATUS Register
Mem Power ON Status
OFFSET: 0x00000014
INSTANCE 0 ADDRESS: 0x40021014
It provides the power status for all the memory banks including- caches, flash (0 and 1) and all the SRAM
groups. The status here should reflect the enable provided by the MEMPWREN register. There may be a
lag time between setting the bits in MEMPWREN register and MEMPWRSTATUS register, due to the need
to cycle the power gate and isolation seqeunces to the memory banks.
2:0 DTCM 0x7 RW
Power up DTCM
NONE = 0x0 - Do not enable power to any DTCMs
GROUP0DTCM0 = 0x1 - Power ON only GROUP0_DTCM0
GROUP0DTCM1 = 0x2 - Power ON only GROUP0_DTCM1
GROUP0 = 0x3 - Power ON only DTCMs in group0
GROUP1 = 0x4 - Power ON only DTCMs in group1
ALL = 0x7 - Power ON all DTCMs
Table 17: MEMPWRSTATUS Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
CACHEB2 CACHEB0
FLASH1 FLASH0
SRAM9 SRAM8 SRAM7 SRAM6 SRAM5 SRAM4 SRAM3 SRAM2 SRAM1 SRAM0 DTCM1
DTCM01 DTCM00
Table 18: MEMPWRSTATUS Register Bits
Bit Name Reset RW Description
31:17 RSVD 0x0 RO
This bitfield is reserved for future use.
16 CACHEB2 0x0 RO
This bit is 1 if power is supplied to Cache Bank 2
15 CACHEB0 0x0 RO
This bit is 1 if power is supplied to Cache Bank 0
14 FLASH1 0x1 RO
This bit is 1 if power is supplied to FLASH 1
13 FLASH0 0x1 RO
This bit is 1 if power is supplied to FLASH 0
12 SRAM9 0x1 RO
This bit is 1 if power is supplied to SRAM GROUP9
11 SRAM8 0x1 RO
This bit is 1 if power is supplied to SRAM GROUP8
Table 16: MEMPWREN Register Bits
Bit Name Reset RW Description