User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 84 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
Table 15: MEMPWREN Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CACHEB2 CACHEB0
RSVD
FLASH1 FLASH0
SRAM DTCM
Table 16: MEMPWREN Register Bits
Bit Name Reset RW Description
31 CACHEB2 0x1 RW
Power up Cache Bank 2. This works in conjunction with Cache enable from
flash_cache module. To power up cache bank2, cache has to be enabled
and this bit has to be set.
EN = 0x1 - Power up Cache Bank 2
DIS = 0x0 - Power down Cache Bank 2
30 CACHEB0 0x1 RW
Power up Cache Bank 0. This works in conjunction with Cache enable from
flash_cache module. To power up cache bank0, cache has to be enabled
and this bit has to be set.
EN = 0x1 - Power up Cache Bank 0
DIS = 0x0 - Power down Cache Bank 0
29:15 RSVD 0x0 RO
RESERVED.
14 FLASH1 0x1 RW
Power up Flash1
EN = 0x1 - Power up Flash1
DIS = 0x0 - Power down Flash1
13 FLASH0 0x1 RW
Power up Flash0
EN = 0x1 - Power up Flash0
DIS = 0x0 - Power down Flash0
12:3 SRAM 0x3ff RW
Power up SRAM groups
NONE = 0x0 - Do not power ON any of the SRAM banks
GROUP0 = 0x1 - Power ON only SRAM group0 (0KB-32KB)
GROUP1 = 0x2 - Power ON only SRAM group1 (32KB-64KB)
GROUP2 = 0x4 - Power ON only SRAM group2 (64KB-96KB)
GROUP3 = 0x8 - Power ON only SRAM group3 (96KB-128KB)
GROUP4 = 0x10 - Power ON only SRAM group4 (128KB-160KB)
GROUP5 = 0x20 - Power ON only SRAM group5 (160KB-192KB)
GROUP6 = 0x40 - Power ON only SRAM group6 (192KB-224KB)
GROUP7 = 0x80 - Power ON only SRAM group7 (224KB-256KB)
GROUP8 = 0x100 - Power ON only SRAM group8 (256KB-288KB)
GROUP9 = 0x200 - Power ON only SRAM group9 (288KB-320KB)
SRAM32K = 0x1 - Power ON only lower 32k
SRAM64K = 0x3 - Power ON only lower 64k
SRAM128K = 0xF - Power ON only lower 128k
SRAM256K = 0xFF - Power ON only lower 256k
ALL = 0x3FF - All SRAM banks (320K) powered ON