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Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 83 of 909 2019 Ambiq Micro, Inc.

3.5.3.1.2.5MEMPWREN Register

Enables individual banks of the MEMORY array

OFFSET: 0x00000010

INSTANCE 0 ADDRESS: 0x40021010

This register enables the individual banks for the memories. When set, power will be enabled to the banks.

This register works in conjection with the MEMPWDINSLEEP register. When this register is set, then the

MEMPWRINSLEEP register will determine whether power is enabled to the SRAMs in deep sleep. If this

FLASH0PWD-

SLP

0x1 RW

Powerdown flash0 in deep sleep

EN = 0x1 - Flash0 is powered down during deepsleep

DIS = 0x0 - Flash0 is kept powered on during deepsleep

12:3 SRAMPWDSLP 0x0 RW

Selects which SRAM banks are powered down in deep sleep mode, causing

the contents of the bank to be lost.

NONE = 0x0 - All banks retained

GROUP0 = 0x1 - SRAM GROUP0 powered down (64KB-96KB)

GROUP1 = 0x2 - SRAM GROUP1 powered down (96KB-128KB)

GROUP2 = 0x4 - SRAM GROUP2 powered down (128KB-160KB)

GROUP3 = 0x8 - SRAM GROUP3 powered down (160KB-192KB)

GROUP4 = 0x10 - SRAM GROUP4 powered down (192KB-224KB)

GROUP5 = 0x20 - SRAM GROUP5 powered down (224KB-256KB)

GROUP6 = 0x40 - SRAM GROUP6 powered down (256KB-288KB)

GROUP7 = 0x80 - SRAM GROUP7 powered down (288KB-320KB)

GROUP8 = 0x100 - SRAM GROUP8 powered down (320KB-352KB)

GROUP9 = 0x200 - SRAM GROUP9 powered down (352KB-384KB)

SRAM32K = 0x1 - Powerdown lower 32k SRAM (64KB-96KB)

SRAM64K = 0x3 - Powerdown lower 64k SRAM (64KB-128KB)

SRAM128K = 0xF - Powerdown lower 128k SRAM (64KB-192KB)

ALLBUTLOWER32K = 0x3FE - All SRAM banks but lower 32k powered

down (96KB-384KB).

ALLBUTLOWER64K = 0x3FC - All banks but lower 64k powered down.

ALLBUTLOWER128K = 0x3F0 - All banks but lower 128k powered down.

ALL = 0x3FF - All banks powered down.

2:0 DTCMPWDSLP 0x0 RW

power down DTCM in deep sleep

NONE = 0x0 - All DTCM retained

GROUP0DTCM0 = 0x1 - Group0_DTCM0 powered down in deep sleep

(0KB-8KB)

GROUP0DTCM1 = 0x2 - Group0_DTCM1 powered down in deep sleep

(8KB-32KB)

GROUP0 = 0x3 - Both DTCMs in group0 are powered down in deep sleep

(0KB-32KB)

ALLBUTGROUP0DTCM0 = 0x6 - Group1 and Group0_DTCM1 are pow-

ered down in deep sleep (8KB-64KB)

GROUP1 = 0x4 - Group1 DTCM powered down in deep sleep (32KB-64KB)

ALL = 0x7 - All DTCMs powered down in deep sleep (0KB-64KB)

Table 14: MEMPWDINSLEEP Register Bits

Bit Name Reset RW Description