User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 80 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
3.5.3.1.2.3DEVPWREN Register
Device Power Enables
OFFSET: 0x00000008
INSTANCE 0 ADDRESS: 0x40021008
This enables various peripherals power domains.
Table 9: SUPPLYSTATUS Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
BLEBUCKON
SIMOBUCKON
Table 10: SUPPLYSTATUS Register Bits
Bit Name Reset RW Description
31:2 RSVD 0x0 RO
RESERVED.
1 BLEBUCKON 0x0 RO
Indicates whether the BLE (if supported) domain and burst (if supported)
domain is supplied from the LDO or the Buck. Buck will be powered up only
if there is an active request for BLEH domain or Burst mode and appropriate
reature is allowed.
LDO = 0x0 - Indicates the the LDO is supplying the BLE/Burst power
domain
BUCK = 0x1 - Indicates the the Buck is supplying the BLE/Burst power
domain
0 SIMOBUCKON 0x0 RO
Indicates whether the Core/Mem low-voltage domains are supplied from the
LDO or the Buck.
OFF = 0x0 - Indicates the the SIMO Buck is OFF.
ON = 0x1 - Indicates the the SIMO Buck is ON.
Table 11: DEVPWREN Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PWRBLEL
PWRPDM
PWRMSPI
PWRSCARD
PWRADC
PWRUART1
PWRUART0
PWRIOM5
PWRIOM4
PWRIOM3
PWRIOM2
PWRIOM1
PWRIOM0
PWRIOS