User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 789 of 909 2019 Ambiq Micro, Inc.
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21.13 Serial Peripheral Interface (SPI) Master Interface
Figure 98. SPI Master Mode, Phase = 0
Table 1156: Serial Peripheral Interface (SPI) Master Interface
Symbol Parameter Min Typ Max Unit
F
SCLK
SCLK frequency range - 8 24 MHz
B
FIFO
FIFO size 32 Bytes
T
SCLK_LO
Clock low time
1/2F
S-
CLK(max)
-- s
T
SCLK_HI
Clock high time
1/2F
S-
CLK(max)
-- s
T
SU_MI
MISO input data setup time - - - ns
T
HD_MI
MISO input data hold time - - - ns
T
HD_MO
MOSI output data hold time - - - ns
T
VALID,MO
MOSI output data valid time - - - ns
SCLK
MISO
T
SU_MI
T
SCLK_HI
T
SCL K_LO
1/F
SCL K
T
VALID_MO
T
HD_MO
MOSI
T
HD_MI
SPOL=0
SPOL=1