User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 78 of 909 2019 Ambiq Micro, Inc.
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status register. The power controller also supports event notification to indicate peripheral power transition
completion. Event notification is the preferred power-optimized method in lieu of status polling.
The power controller is also the primary control block for the BLE/Burst and SIMO Buck converters as well
as the LDO regulators when Bucks are disabled. Similarly, event notification is supported to provide the
appropriate handshake to software as needed as well as status register indicators.
This block handles all power sequencing during initial power on and all power mode transitions.
3.5.3.1 PWRCTRL Registers
PWR Controller Register Bank
INSTANCE 0 BASE ADDRESS:0x40021000
Power Controller register Bank - this is the place SW writes to.
3.5.3.1.1 Register Memory Map
Table 6: PWRCTRL Register Map
Address(s) Register Name Description
0x40021000 SUPPLYSRC Voltage Regulator Select Register
0x40021004 SUPPLYSTATUS Voltage Regulators status
0x40021008 DEVPWREN Device Power Enables
0x4002100C MEMPWDINSLEEP Powerdown SRAM banks in Deep Sleep mode
0x40021010 MEMPWREN Enables individual banks of the MEMORY array
0x40021014 MEMPWRSTATUS Mem Power ON Status
0x40021018 DEVPWRSTATUS Device Power ON Status
0x4002101C SRAMCTRL SRAM Control register
0x40021020 ADCSTATUS Power Status Register for ADC Block
0x40021024 MISC Power Optimization Control Bits
0x40021028 DEVPWREVENTEN
Event enable register to control which DEVP-
WRSTATUS bits are routed to event input of
CPU.
0x4002102C MEMPWREVENTEN
Event enable register to control which MEMP-
WRSTATUS bits are routed to event input of
CPU.