User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 777 of 909 2019 Ambiq Micro, Inc.
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I
SDS2-384RET
System Deep
Sleep mode 2 cur-
rent w/ 384kB
retention
WFI instruction with SLEEPDEEP=1, XTAL
ON, buck converters enabled in LP mode,
all I/O power domains powered OFF, BLE
OFF, 384kB SRAM in retention
3.3v 2.7 μA
1.8v 3.7 μA
I
SDS2-8RET
System Deep
Sleep mode 2 cur-
rent w/ 8kB reten-
tion
WFI instruction with SLEEPDEEP=1, XTAL
ON, buck converters enabled in LP mode,
all I/O power domains powered OFF, BLE
OFF, 8kB SRAM in retention
3.3v 1.4 μA
1.8v 0.98 μA
I
SDS3
System Deep
Sleep mode 3 cur-
rent
WFI instruction with SLEEPDEEP=1, XTAL
OFF, buck converters enabled in LP mode,
all I/O power domains powered OFF, BLE
OFF, all SRAM OFF
3.3v 1.2 μA
1.8v 0.8 μA
BLE Operating Current
I
Active_Rx
Radio Rx current
3.3V TBD 3.0 TBD mA
I
Active_Tx
Radio Tx current Measured at 0 dBm
3.3V TBD 3.0 TBD mA
ADC Operating Current
c
I
AD-
C_RUN_LPM0
ADC run mode low
power mode 0
Average run current (LPMODE0: max con-
version rate, single slot, 14-bit, CPU in
deep sleep otherwise with 16kB SRAM and
cache in retention. ADC / gated domains
ON. All other IO domains OFF
3.3 V µA
I
AD-
C_RUN_LPM1
ADC run mode low
power mode 1
Average run current (LPMODE1: 1kHz
sample period, single slot, 14-bit, CPU in
deep sleep otherwise with 16kB SRAM and
cache in retention, main ADC power
domain ON. HW controlled ADC gated
domain duty cycled between samples.
3.3 V µA
I
AD-
C_RUN_LPM2
ADC run mode low
power mode 2
Average run current (LPMODE2: 10Hz
sample period, single slot, 14-bit, CPU in
deep sleep otherwise with 16kB SRAM and
cache in retention, main ADC power
domain duty cycled by software with cali-
bration each sample conversion
3.3 V µA
Flash Memory Operating Current
I
PROGRAM
Supply current
during a page pro-
gram
3.3 V TBD mA
I
ERASE
Supply current
during a page
erase
3.3 V TBD mA
I
MASSERASE
Supply current
during a mass
erase
3.3 V TBD mA
a. Core clock (HCLK) is 48 MHz for each parameter unless otherwise noted.
b. All values measured at 25°C
c. Base SoC power state is S
DS2
with minimal SRAM retention. Current represents total current at battery.
Table 1145: Current Consumption