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Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 77 of 909 2019 Ambiq Micro, Inc.

▪ 384KB: S

DS1-384RET

▪ 256KB: S

DS1-256RET

▪ 128KB: S

DS1-128RET

▪ 64KB: S

DS1-64RET

▪ 8KB: S

DS1-8RET

▪ 0KB: S

DS1

3.5.2.7 SYS Deep Sleep Mode 2 (S

DS2

)

In SYS Deep Sleep Mode 2, this is the minimum power state that the MCU can resume normal operation.

In this mode, minimal SRAM memory is retained as needed for software to resume (note that SRAM can

have 0-384 KB in retention depending on the software/system functional and latency requirements),

Cache is powered off (no retention), Flash memory is in power down, HFRC is off, XTAL is ON, all internal

switched power domains are off/gated. CPU is in Deep Sleep. Core logic state is retained.

Note: For easier notation, SRAM memory retention is defined as follows:

▪ 384KB: S

DS2-384RET

▪ 256KB: S

DS2-256RET

▪ 128KB: S

DS2-128RET

▪ 64KB: S

DS2-64RET

▪ 8KB: S

DS2-8RET

▪ 0KB: S

DS2

This state can be entered when all activity has suspended for a duration of time sufficient to sustain the

longer exit latencies to resume. This could be a state where periodic data samples are taken and the data

is locally processed/accumulated/transferred at long time intervals. This state can only be entered (vs

DS1

) if the peripheral devices are either not enabled/active or if the application can afford to save/restore

the state of the controller(s) on entry/exit of this mode.

3.5.2.8 SYS Deep Sleep Mode 3 (S

DS3

)

In SYS Deep Sleep Mode 3, this is a deep sleep power state for the MCU. In this mode, no memory is in

retention, all memory is powered down, LFRC is on (HFRC and XTAL are off), all internal switched power

domains are off/gated. CPU is in Deep Sleep. Core logic state is retained. Single timer is running.

This state can be entered on long inactivity periods. Also can be used for very low power ADC sampling

without CPU interaction.

3.5.2.9 SYS OFF Mode (S

OFF

)

In SYS OFF Mode, MCU is completely powered down with no power supplied. CPU is in shutdown mode

with no state retention. Only Flash memory is retained.

This mode is controlled external to the MCU by removing power to the device.

3.5.3 Power Control

Power control block provides control and status for the power state of all the power domains, voltage

regulators in the SoC. Software can control these blocks via power control registers within this block.

The power control block controls the power sequence to power up or down a particular peripheral device

and memory power domain. Status of each of these can be monitored in the respective power control