User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 767 of 909 2019 Ambiq Micro, Inc.
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19.2.2.2 STAT Register
Status Register
OFFSET: 0x00000004
INSTANCE 0 ADDRESS: 0x4000C004
Status Register
19.2.2.3 PWDKEY Register
Key Register for Powering Down the Voltage Comparator
OFFSET: 0x00000008
INSTANCE 0 ADDRESS: 0x4000C008
1:0 PSEL 0x0 RW
This bitfield selects the positive input to the comparator.
VDDADJ = 0x0 - Use VDDADJ for the positive input.
VTEMP = 0x1 - Use the temperature sensor output for the positive input.
Note: If this channel is selected for PSEL, the bandap circuit required for
temperature comparisons will automatically turn on. The bandgap circuit
requires 11us to stabalize.
VEXT1 = 0x2 - Use external voltage 0 for positive input.
VEXT2 = 0x3 - Use external voltage 1 for positive input.
Table 1131: STAT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PWDSTAT
CMPOUT
Table 1132: STAT Register Bits
Bit Name Reset RW Description
31:2 RSVD 0x0 RO
This bitfield is reserved for future use.
1PWDSTAT 0x0RO
This bit indicates the power down state of the voltage comparator.
POWERED_DOWN = 0x1 - The voltage comparator is powered down.
0CMPOUT 0x0RO
This bit is 1 if the positive input of the comparator is greater than the nega-
tive input.
VOUT_LOW = 0x0 - The negative input of the comparator is greater than
the positive input.
VOUT_HIGH = 0x1 - The positive input of the comparator is greater than the
negative input.
Table 1130: CFG Register Bits
Bit Name Reset RW Description