User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 761 of 909 2019 Ambiq Micro, Inc.
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DMABCOUNT Register
DMA Burst Transfer Count
OFFSET: 0x00000284
INSTANCE 0 ADDRESS: 0x50010284
DMA Burst Transfer Count
18 DPWROFF 0x0 RW
Power Off the ADC System upon DMACPL.
17 DMAMSK 0x0 RW
Mask the FIFOCNT and SLOTNUM when transferring FIFO contents to
memory
DIS = 0x0 - FIFO Contents are copied directly to memory without modifica-
tion.
EN = 0x1 - Only the FIFODATA contents are copied to memory on DMA
transfers. The SLOTNUM and FIFOCNT contents are cleared to zero.
16 RSVD 0x0 RO RESERVED
15:10 RSVD 0x0 RO
RESERVED.
9 DMADYNPRI 0x0 RW
Enables dynamic priority based on FIFO fullness. When FIFO is full, priority
is automatically set to HIGH. Otherwise, DMAPRI is used.
DIS = 0x0 - Disable dynamic priority (use DMAPRI setting only)
EN = 0x1 - Enable dynamic priority
8 DMAPRI 0x0 RW
Sets the Priority of the DMA request
LOW = 0x0 - Low Priority (service as best effort)
HIGH = 0x1 - High Priority (service immediately)
7:3 RSVD 0x0 RO
RESERVED.
2 DMADIR 0x0 RO
Direction
P2M = 0x0 - Peripheral to Memory (SRAM) transaction
M2P = 0x1 - Memory to Peripheral transaction
1 RSVD 0x0 RO
RESERVED.
0 DMAEN 0x0 RW
DMA Enable
DIS = 0x0 - Disable DMA Function
EN = 0x1 - Enable DMA Function
Table 1120: DMABCOUNT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
Table 1119: DMACFG Register Bits
Bit Name Reset RW Description