User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 76 of 909 2019 Ambiq Micro, Inc.
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3.5.2.3 SYS Sleep Mode 0 (S
S0
)
In SYS Sleep Mode 0, this is a low power state for the MCU. In this mode, all SRAM memory is retained
(up to 384KB), Flash memory is in standby, HFRC is on, main core clock domain is gated but peripheral
clock domains can be on. CPU is in Sleep Mode.
This state can be entered if a peripheral device (such as SPI/UART/I2C) is actively transferring data and
the time window is sufficient for CPU to enter Sleep Mode but is not long enough to go into a Deep Sleep
Mode.
3.5.2.4 SYS Sleep Mode 1 (S
S1
)
In SYS Sleep Mode 1, this is a low power state for the MCU. In this mode, all SRAM memory is retained
(up to 384 KB), Flash memory is in standby, HFRC is on, all functional clocks are gated. CPU is in Sleep
Mode.
This state can be entered if a no peripheral device (SPI/UART/I2C/MSPI/SCARD/BLE) is actively
transferring data, however, communication may occur within a short time window which will prevent the
CPU from entering Deep Sleep Mode (and subsequently the system from entering a lower power state).
This state is also referred to as “Active Idle”. In other words, all power domains are powered on, but all
clocks are gated. This state is a good power baseline for the system as it represents the active mode DC
power level. Typically the power in this state is dominated by leakage and always-on functional blocks.
3.5.2.5 SYS Deep Sleep Mode 0 (S
DS0
)
In SYS Deep Sleep Mode 0, this is a deep low power state for the MCU. In this mode, SRAM is in retention
(capacity controlled by software), cache memory is in retention (16 KB), Flash memory is in power down,
HFRC is on, main core power domain is off but peripheral power domains can be on. CPU is in Deep
Sleep. Core logic state is retained.
This state can be entered if a peripheral device (SPI/UART/I2C/MSPI/SCARD/BLE) is actively (or
intermittently) transferring data but the window of acquisition is long enough to allow the CPU to go into a
deeper low power state.
Note: For easier notation, SRAM memory retention is defined as follows:
▪ 384KB: S
DS0-384RET
▪ 256KB: S
DS0-256RET
▪ 128KB: S
DS0-128RET
▪ 64KB: S
DS0-64RET
▪ 8KB: S
DS0-8RET
▪ 0KB: S
DS0
3.5.2.6 SYS Deep Sleep Mode 1 (S
DS1
)
In SYS Deep Sleep Mode 1, this is a deep low power state for the MCU. In this mode, SRAM is in retention
(capacity controlled by software), cache memory is powered down, Flash memory is in power down, HFRC
is on, main core power domain is off but peripheral power domains can be on. CPU is in Deep Sleep. Core
logic state is retained.
This state can be entered if the latency to warm up the cache can be tolerated. This could be an extended
wait for peripheral communication event.
Note: For easier notation, SRAM memory retention is defined as follows: