User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 759 of 909 2019 Ambiq Micro, Inc.
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DMATRIGEN Register
DMA Trigger Enable Register
OFFSET: 0x00000240
INSTANCE 0 ADDRESS: 0x50010240
DMA Trigger Enable Register
DMATRIGSTAT Register
DMA Trigger Status Register
OFFSET: 0x00000244
4 WCEXC 0x0 RW
Window comparator voltage excursion interrupt.
WCEXCINT = 0x1 - Window comparator voltage excursion interrupt.
3 FIFOOVR2 0x0 RW
FIFO 100 percent full interrupt.
FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.
2 FIFOOVR1 0x0 RW
FIFO 75 percent full interrupt.
FIFO75INT = 0x1 - FIFO 75 percent full interrupt.
1 SCNCMP 0x0 RW
ADC scan complete interrupt.
SCNCMPINT = 0x1 - ADC scan complete interrupt.
0 CNVCMP 0x0 RW
ADC conversion complete interrupt.
CNVCMPINT = 0x1 - ADC conversion complete interrupt.
Table 1114: DMATRIGEN Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
DFIFOFULL
DFIFO75
Table 1115: DMATRIGEN Register Bits
Bit Name Reset RW Description
31:2 RSVD 0x0 RO
RESERVED.
1 DFIFOFULL 0x0 RW
Trigger DMA upon FIFO 100& Full
0 DFIFO75 0x0 RW
Trigger DMA upon FIFO 75 percent Full
Table 1113: INTSET Register Bits
Bit Name Reset RW Description