User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 758 of 909 2019 Ambiq Micro, Inc.
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INTSET Register
ADC Interrupt registers: Set
OFFSET: 0x0000020C
INSTANCE 0 ADDRESS: 0x5001020C
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for
testing purposes).
3 FIFOOVR2 0x0 RW
FIFO 100 percent full interrupt.
FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.
2 FIFOOVR1 0x0 RW
FIFO 75 percent full interrupt.
FIFO75INT = 0x1 - FIFO 75 percent full interrupt.
1 SCNCMP 0x0 RW
ADC scan complete interrupt.
SCNCMPINT = 0x1 - ADC scan complete interrupt.
0 CNVCMP 0x0 RW
ADC conversion complete interrupt.
CNVCMPINT = 0x1 - ADC conversion complete interrupt.
Table 1112: INTSET Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
DERR
DCMP
WCINC
WCEXC
FIFOOVR2 FIFOOVR1
SCNCMP CNVCMP
Table 1113: INTSET Register Bits
Bit Name Reset RW Description
31:8 RSVD 0x0 RO
RESERVED.
7DERR 0x0RW
DMA Error Condition
DMAERROR = 0x1 - DMA Error Condition Occurred
6 DCMP 0x0 RW
DMA Transfer Complete
DMACOMPLETE = 0x1 - DMA Completed a transfer
5 WCINC 0x0 RW
Window comparator voltage incursion interrupt.
WCINCINT = 0x1 - Window comparator voltage incursion interrupt.
Table 1111: INTCLR Register Bits
Bit Name Reset RW Description