User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 755 of 909 2019 Ambiq Micro, Inc.
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INTEN Register
ADC Interrupt registers: Enable
OFFSET: 0x00000200
INSTANCE 0 ADDRESS: 0x50010200
Set bits in this register to allow this module to generate the corresponding interrupt.
Table 1105: FIFOPR Register Bits
Bit Name Reset RW Description
31 RSVDPR 0x0 RO
RESERVED.
30:28 SLOTNUMPR 0x0 RO
Slot number associated with this FIFO data.
27:20 COUNT 0x0 RO
Number of valid entries in the ADC FIFO.
19:0 DATA 0x0 RO
Oldest data in the FIFO.
Table 1106: INTEN Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
DERR
DCMP
WCINC
WCEXC
FIFOOVR2 FIFOOVR1
SCNCMP CNVCMP
Table 1107: INTEN Register Bits
Bit Name Reset RW Description
31:8 RSVD 0x0 RO
RESERVED.
7DERR 0x0RW
DMA Error Condition
DMAERROR = 0x1 - DMA Error Condition Occurred
6 DCMP 0x0 RW
DMA Transfer Complete
DMACOMPLETE = 0x1 - DMA Completed a transfer
5 WCINC 0x0 RW
Window comparator voltage incursion interrupt.
WCINCINT = 0x1 - Window comparator voltage incursion interrupt.
4 WCEXC 0x0 RW
Window comparator voltage excursion interrupt.
WCEXCINT = 0x1 - Window comparator voltage excursion interrupt.