User Manual

Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 75 of 909 2019 Ambiq Micro, Inc.

will be wrong when using Burst Mode. It is recommended not to use SYSTICK and Burst Mode together

unless proper compensation is made.

3.5.1.2 Active Mode

In the Active Mode, the M4 is powered up, clocks are active, and instructions are being executed. In this

mode, the M4 expects all (enabled) devices attached to the AHB and APB to be powered and clocked for

normal access. All of the non-debug ARM clocks (FCLK, HCLK) are active in this state.

To transition from the Active Mode to any of the lower-power modes, a specific sequence of instructions is

executed on the M4 core. First, specific bits in the ARMv7-M System Control Register must be set to

determine the mode to enter. See page B3-269 of the ARMv7-M Architecture Reference Manual for more

details.

After the SCR is setup, code can enter the low-power states using one of the 3 following methods:

▪ Execute a Wait-For-Interrupt (WFI) instruction.

▪ Execute a Wait-For-Event (WFE) instruction.

▪ Set the SLEEPONEXIT bit of the SCR such that the exit from an ISR will automatically return to a sleep

state.

The M4 will enter a low-power mode after one of these are performed (assuming all conditions are met)

and remain there until some event causes the core to return to Active Mode. The possible reasons to

return to Active Mode are:

▪ A reset

▪ An enabled Interrupt is received by the NVIC

▪ An event is received by the NVIC

▪ A Debug Event is received from the DAP

3.5.1.3 Sleep Mode

In the Sleep Mode, the M4 is powered up, but the clocks (HCLK, FCLK) are not active. The power supply

is still applied to the M4 logic such that it can immediately become active on a wakeup event and begin

executing instructions.

3.5.1.4 Deep Sleep Mode

In the Deep Sleep Mode, the M4 enters SRPG mode where the main power is removed, but the flops

retain their state. The clocks are not active, and the MCU clock sources for HCLK and FCLK can be

deactivated. To facilitate the removal of the source supply and entry into SRPG mode, the M4 will

handshake with the Wake-up Interrupt Controller and Power Management Unit and set up the possible

wakeup conditions.

3.5.2 System Power Modes

In addition to the CPU power states, there are system power states defined as follows.

3.5.2.1 SYS Active Burst (S

ACTB

)

CPU is in Active Burst Mode and executing instructions. All peripheral devices are on and available.

3.5.2.2 SYS Active (S

ACT

)

CPU is in Active Mode and executing instructions. All peripheral devices are on and available.