User Manual

Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 74 of 909 2019 Ambiq Micro, Inc.

You can use the MPU to:

▪ Enforce privilege rules.

▪ Separate processes.

▪ Enforce access rules.

3.4 System Busses

The ARM Cortex-M4 utilizes 3 instances of the AMBA AHB bus for communication with memory and

peripherals. The ICode bus is designed for instruction fetches from the ‘Code’ memory space while the

DCode bus is designed for data and debug accesses in that same region. The System bus is designed for

fetches to the SRAM and other peripheral devices of the MCU.

The Apollo3 Blue MCU maps the available SRAM memory onto an address space within the ‘Code’

memory space. This gives the user the opportunity to perform instruction and data fetches from the lower-

power SRAM to effectively lower the power consumption of the MCU.

The peripherals of the Apollo3 Blue MCU which are infrequently accessed are located on an AMBA APB

bus. A bridge exists which translates the accesses from the System AHB to the APB. Accesses to these

peripherals will inject a single wait-state on the AHB during any access cycle.

3.5 Power Management

The Power Management Unit (PMU) is a finite-state machine that controls the transitions of the MCU

between power modes. When moving from Active Mode to Deep Sleep Mode, the PMU manages the

state-retention capability of the registers within the Cortex-M4 core and also controls the shutdown of the

voltage regulators of the MCU. Once in the Deep Sleep Mode, the PMU, in conjunction with the Wake-Up

Interrupt Controller, waits for a wakeup event. When the event is observed, the PMU begins the power

restoration process by re-enabling the on-chip voltage regulators and restoring the CPU register state. The

M4 is then returned to active mode once all state is ready.

The Apollo3 Blue MCU power modes are described in the subsequent discussion along with the operation

of the PMU.

3.5.1 Cortex-M4 Power Modes

The ARM Cortex-M4 defines the following 3 power modes:

▪ Active

▪ Sleep

▪ Deep Sleep

In addition to the above ARM-defined modes, the Apollo3 Blue MCUwill support a Shutdown mode in

which the entire device is powered down except for the logic required to support a Power-On Reset.

Each mode is described below.

3.5.1.1 Burst Mode

The Apollo3 Blue MCU supports the Ambiq TurboSPOT which enables a higher frequency operating mode

(Burst Mode). In this mode, the M4 and all memory run at an elevated frequency. All of the non-debug

ARM clocks (FCLK, HCLK) also operate at the elevated frequency level. All peripherals are maintained at

the nominal frequency level during burst. This mode is entered and exited under software direction but

transitions are completely handled in hardware.

NOTE

In Burst Mode on the Apollo3 Blue MCU, the SYSTICK increments at twice the normal (48 MHz) clock rate.

Some RTOSes may use SYSTICK for scheduler timing by default, in which case scheduler event timing