User Manual

Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 737 of 909 2019 Ambiq Micro, Inc.

ADC Registers

CFG Register

Configuration Register

OFFSET: 0x00000000

INSTANCE 0 ADDRESS: 0x50010000

The ADC Configuration Register contains the software control for selecting the clock frequency used for

the SAR conversions, the trigger polarity, the trigger select, the reference voltage select, the low power

mode, the operating mode (single scan per trigger vs. repeating mode) and ADC enable.

0x50010014 SL2CFG Slot 2 Configuration Register

0x50010018 SL3CFG Slot 3 Configuration Register

0x5001001C SL4CFG Slot 4 Configuration Register

0x50010020 SL5CFG Slot 5 Configuration Register

0x50010024 SL6CFG Slot 6 Configuration Register

0x50010028 SL7CFG Slot 7 Configuration Register

0x5001002C WULIM Window Comparator Upper Limits Register

0x50010030 WLLIM Window Comparator Lower Limits Register

0x50010038 FIFO FIFO Data and Valid Count Register

0x5001003C FIFOPR FIFO Data and Valid Count Register

0x50010200 INTEN ADC Interrupt registers: Enable

0x50010204 INTSTAT ADC Interrupt registers: Status

0x50010208 INTCLR ADC Interrupt registers: Clear

0x5001020C INTSET ADC Interrupt registers: Set

0x50010240 DMATRIGEN DMA Trigger Enable Register

0x50010244 DMATRIGSTAT DMA Trigger Status Register

0x50010280 DMACFG DMA Configuration Register

0x50010284 DMABCOUNT DMA Burst Transfer Count

0x50010288 DMATOTCOUNT DMA Total Transfer Count

0x5001028C DMATARGADDR DMA Target Address Register

0x50010290 DMASTAT DMA Status Register

Table 1075: ADC Register Map

Address(s) Register Name Description