User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 73 of 909 2019 Ambiq Micro, Inc.
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3.3 Memory Protection Unit (MPU)
The Apollo3 Blue MCU includes an MPU which is a core component for memory protection. The M4
processor supports the standard ARMv7 Protected Memory System Architecture model. The MPU
provides full support for:
▪ Protection regions.
▪ Overlapping protection regions, with ascending region priority:
- 7 = highest priority
- 0 = lowest priority.
▪ Access permissions
▪ Exporting memory attributes to the system.
MPU mismatches and permission violations invoke the programmable-priority MemManage fault handler.
See the ARM
®
v7-M Architecture Reference Manual for more information.
0x50007000 – 0x50007FFF
I
2
C / SPI Master3
0x50008000 – 0x50008FFF
I
2
C / SPI Master4
0x50009000 – 0x50009FFF
I
2
C / SPI Master5
0x5000A000 – 0x5000BFFF Reserved
0x5000C000 – 0x5000CFFF BLE
0x5000D000 – 0x5000FFFF Reserved
0x50010000 – 0x500103FF ADC
0x50010400 – 0x50010FFF Reserved
0x50011000 – 0x500113FF PDM
0x50011400 – 0x50013FFF Reserved
0x50014000 – 0x500143FF MSPI Master
0x50014400 – 0x5001FFFF Reserved
0x50020000 – 0x5002FFFF Flash OTP
0x50030000 – 0x5FFFFFFF Reserved
0x51000000 – 0x51FFFFFF
XIP MM (Read/Write to External MSPI
Device) [Chip Rev B Only]
Table 5: MCU Peripheral Device Memory Map
Address Device