User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 722 of 909 2019 Ambiq Micro, Inc.
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7FEIC 0x0WO
This bit holds the framing error interrupt clear.
6RTIC 0x0WO
This bit holds the receive timeout interrupt clear.
5TXIC 0x0WO
This bit holds the transmit interrupt clear.
4RXIC 0x0WO
This bit holds the receive interrupt clear.
3DSRMIC 0x0WO
This bit holds the modem DSR interrupt clear.
2 DCDMIC 0x0 WO
This bit holds the modem DCD interrupt clear.
1CTSMIC 0x0WO
This bit holds the modem CTS interrupt clear.
0 TXCMPMIC 0x0 WO
This bit holds the modem TXCMP interrupt clear.
Table 1062: IEC Register Bits
Bit Name Reset RW Description