User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 721 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
17.6.2.13IEC Register
Interrupt Clear
OFFSET: 0x00000044
INSTANCE 0 ADDRESS: 0x4001C044
INSTANCE 1 ADDRESS: 0x4001D044
Interrupt Clear
6RTMIS 0x0RO
This bit holds the receive timeout interrupt status masked.
5TXMIS 0x0RO
This bit holds the transmit interrupt status masked.
4RXMIS 0x0RO
This bit holds the receive interrupt status masked.
3DSRMMIS 0x0RO
This bit holds the modem DSR interrupt status masked.
2 DCDMMIS 0x0 RO
This bit holds the modem DCD interrupt status masked.
1 CTSMMIS 0x0 RO
This bit holds the modem CTS interrupt status masked.
0 TXCMPMMIS 0x0 RO
This bit holds the modem TXCMP interrupt status masked.
Table 1061: IEC Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
OEIC
BEIC PEIC
FEIC
RTIC
TXIC
RXIC
DSRMIC
DCDMIC
CTSMIC
TXCMPMIC
Table 1062: IEC Register Bits
Bit Name Reset RW Description
31:11 RSVD 0x0 RO
This bitfield is reserved for future use.
10 OEIC 0x0 WO
This bit holds the overflow interrupt clear.
9 BEIC 0x0 WO
This bit holds the break error interrupt clear.
8 PEIC 0x0 WO
This bit holds the parity error interrupt clear.
Table 1060: MIS Register Bits
Bit Name Reset RW Description