User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 720 of 909 2019 Ambiq Micro, Inc.
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17.6.2.12MIS Register
Masked Interrupt Status
OFFSET: 0x00000040
INSTANCE 0 ADDRESS: 0x4001C040
INSTANCE 1 ADDRESS: 0x4001D040
Masked Interrupt Status
5TXRIS 0x0RO
This bit holds the transmit interrupt status.
4RXRIS 0x0RO
This bit holds the receive interrupt status.
3DSRMRIS 0x0RO
This bit holds the modem DSR interrupt status.
2 DCDMRIS 0x0 RO
This bit holds the modem DCD interrupt status.
1CTSMRIS 0x0RO
This bit holds the modem CTS interrupt status.
0 TXCMPMRIS 0x0 RO
This bit holds the modem TXCMP interrupt status.
Table 1059: MIS Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
OEMIS
BEMIS PEMIS
FEMIS
RTMIS
TXMIS
RXMIS
DSRMMIS
DCDMMIS
CTSMMIS
TXCMPMMIS
Table 1060: MIS Register Bits
Bit Name Reset RW Description
31:11 RSVD 0x0 RO
This bitfield is reserved for future use.
10 OEMIS 0x0 RO
This bit holds the overflow interrupt status masked.
9 BEMIS 0x0 RO
This bit holds the break error interrupt status masked.
8 PEMIS 0x0 RO
This bit holds the parity error interrupt status masked.
7FEMIS 0x0RO
This bit holds the framing error interrupt status masked.
Table 1058: IES Register Bits
Bit Name Reset RW Description