User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 719 of 909 2019 Ambiq Micro, Inc.
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17.6.2.11IES Register
Interrupt Status
OFFSET: 0x0000003C
INSTANCE 0 ADDRESS: 0x4001C03C
INSTANCE 1 ADDRESS: 0x4001D03C
Interrupt Status
4RXIM 0x0RW
This bit holds the receive interrupt enable.
3DSRMIM 0x0RW
This bit holds the modem DSR interrupt enable.
2 DCDMIM 0x0 RW
This bit holds the modem DCD interrupt enable.
1CTSMIM 0x0RW
This bit holds the modem CTS interrupt enable.
0TXCMPMIM 0x0RW
This bit holds the modem TXCMP interrupt enable.
Table 1057: IES Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
OERIS
BERIS PERIS
FERIS
RTRIS
TXRIS
RXRIS
DSRMRIS
DCDMRIS
CTSMRIS
TXCMPMRIS
Table 1058: IES Register Bits
Bit Name Reset RW Description
31:11 RSVD 0x0 RO
This bitfield is reserved for future use.
10 OERIS 0x0 RO
This bit holds the overflow interrupt status.
9 BERIS 0x0 RO
This bit holds the break error interrupt status.
8 PERIS 0x0 RO
This bit holds the parity error interrupt status.
7FERIS 0x0RO
This bit holds the framing error interrupt status.
6RTRIS 0x0RO
This bit holds the receive timeout interrupt status.
Table 1056: IER Register Bits
Bit Name Reset RW Description