User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 718 of 909 2019 Ambiq Micro, Inc.
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17.6.2.10IER Register
Interrupt Enable
OFFSET: 0x00000038
INSTANCE 0 ADDRESS: 0x4001C038
INSTANCE 1 ADDRESS: 0x4001D038
Interrupt Enable
Table 1054: IFLS Register Bits
Bit Name Reset RW Description
31:6 RSVD 0x0 RO
This bitfield is reserved for future use.
5:3 RXIFLSEL 0x2 RW
These bits hold the receive FIFO interrupt level.
2:0 TXIFLSEL 0x2 RW
These bits hold the transmit FIFO interrupt level.
Table 1055: IER Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
OEIM
BEIM PEIM
FEIM
RTIM
TXIM
RXIM
DSRMIM
DCDMIM
CTSMIM
TXCMPMIM
Table 1056: IER Register Bits
Bit Name Reset RW Description
31:11 RSVD 0x0 RO
This bitfield is reserved for future use.
10 OEIM 0x0 RW
This bit holds the overflow interrupt enable.
9 BEIM 0x0 RW
This bit holds the break error interrupt enable.
8 PEIM 0x0 RW
This bit holds the parity error interrupt enable.
7FEIM 0x0RW
This bit holds the framing error interrupt enable.
6RTIM 0x0RW
This bit holds the receive timeout interrupt enable.
5TXIM 0x0RW
This bit holds the transmit interrupt enable.