User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 717 of 909 2019 Ambiq Micro, Inc.
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17.6.2.9 IFLS Register
FIFO Interrupt Level Select
OFFSET: 0x00000034
INSTANCE 0 ADDRESS: 0x4001C034
INSTANCE 1 ADDRESS: 0x4001D034
FIFO Interrupt Level Select
10 DTR 0x0 RW
This bit enables data transmit ready.
9RXE 0x1RW
This bit is the receive enable.
8TXE 0x1RW
This bit is the transmit enable.
7LBE 0x0RW
This bit is the loopback enable.
6:4 CLKSEL 0x0 RW
This bitfield is the UART clock select.
NOCLK = 0x0 - No UART clock. This is the low power default.
24MHZ = 0x1 - 24 MHz clock.
12MHZ = 0x2 - 12 MHz clock.
6MHZ = 0x3 - 6 MHz clock.
3MHZ = 0x4 - 3 MHz clock.
RSVD5 = 0x5 - Reserved.
RSVD6 = 0x6 - Reserved.
RSVD7 = 0x7 - Reserved.
3 CLKEN 0x0 RW
This bit is the UART clock enable.
2 SIRLP 0x0 RW
This bit is the SIR low power select.
1SIREN 0x0RW
This bit is the SIR ENDEC enable.
0UARTEN 0x0RW
This bit is the UART enable.
Table 1053: IFLS Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
RXIFLSEL
TXIFLSEL
Table 1052: CR Register Bits
Bit Name Reset RW Description