User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 716 of 909 2019 Ambiq Micro, Inc.
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17.6.2.8 CR Register
Control Register
OFFSET: 0x00000030
INSTANCE 0 ADDRESS: 0x4001C030
INSTANCE 1 ADDRESS: 0x4001D030
Control Register
4FEN 0x0RW
This bit holds the FIFO enable.
3STP2 0x0RW
This bit holds the two stop bits select.
2 EPS 0x0 RW
This bit holds the even parity select.
1 PEN 0x0 RW
This bit holds the parity enable.
0BRK 0x0RW
This bit holds the break set.
Table 1051: CR Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
CTSEN
RTSEN
OUT2 OUT1
RTS
DTR RXE
TXE
LBE
CLKSEL
CLKEN
SIRLP
SIREN
UARTEN
Table 1052: CR Register Bits
Bit Name Reset RW Description
31:16 RSVD 0x0 RO
This bitfield is reserved for future use.
15 CTSEN 0x0 RW
This bit enables CTS hardware flow control.
14 RTSEN 0x0 RW
This bit enables RTS hardware flow control.
13 OUT2 0x0 RW
This bit holds modem Out2.
12 OUT1 0x0 RW
This bit holds modem Out1.
11 RTS 0x0 RW
This bit enables request to send.
Table 1050: LCRH Register Bits
Bit Name Reset RW Description