User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 715 of 909 2019 Ambiq Micro, Inc.
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Fractional Baud Rate Divisor
17.6.2.7 LCRH Register
Line Control High
OFFSET: 0x0000002C
INSTANCE 0 ADDRESS: 0x4001C02C
INSTANCE 1 ADDRESS: 0x4001D02C
Line Control High
Table 1047: FBRD Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD DIVFRAC
Table 1048: FBRD Register Bits
Bit Name Reset RW Description
31:6 RSVD 0x0 RO
This bitfield is reserved for future use.
5:0 DIVFRAC 0x0 RW
These bits hold the baud fractional divisor.
Table 1049: LCRH Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
SPS
WLEN
FEN
STP2
EPS
PEN BRK
Table 1050: LCRH Register Bits
Bit Name Reset RW Description
31:8 RSVD 0x0 RO
This bitfield is reserved for future use.
7 SPS 0x0 RW
This bit holds the stick parity select.
6:5 WLEN 0x0 RW
These bits hold the write length.
WLEN Data Bits
00 5
01 6
10 7
11 8