User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 713 of 909 2019 Ambiq Micro, Inc.
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17.6.2.4 ILPR Register
IrDA Counter
OFFSET: 0x00000020
INSTANCE 0 ADDRESS: 0x4001C020
INSTANCE 1 ADDRESS: 0x4001D020
IrDA Counter
Table 1041: FR Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
TXBUSY
TXFE
RXFF
TXFF
RXFE
BUSY
DCD
DSR
CTS
Table 1042: FR Register Bits
Bit Name Reset RW Description
31:9 RSVD 0x0 RO
This bitfield is reserved for future use.
8TXBUSY 0x0RO
This bit holds the transmit BUSY indicator.
7TXFE 0x0RO
This bit holds the transmit FIFO empty indicator.
XMTFIFO_EMPTY = 0x1 - Transmit fifo is empty.
6RXFF 0x0RO
This bit holds the receive FIFO full indicator.
RCVFIFO_FULL = 0x1 - Receive fifo is full.
5TXFF 0x0RO
This bit holds the transmit FIFO full indicator.
XMTFIFO_FULL = 0x1 - Transmit fifo is full.
4RXFE 0x0RO
This bit holds the receive FIFO empty indicator.
RCVFIFO_EMPTY = 0x1 - Receive fifo is empty.
3 BUSY 0x0 RO
This bit holds the busy indicator.
BUSY = 0x1 - UART busy indicator.
2DCD 0x0RO
This bit holds the data carrier detect indicator.
DETECTED = 0x1 - Data carrier detect detected.
1DSR 0x0RO
This bit holds the data set ready indicator.
READY = 0x1 - Data set ready.
0CTS 0x0RO
This bit holds the clear to send indicator.
CLEARTOSEND = 0x1 - Clear to send is indicated.