User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 709 of 909 2019 Ambiq Micro, Inc.
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The UART Module supports independent CTS and RTS hardware flow control. All flow control
configuration may be set using the UART_CR register.
17.5 Transmit FIFO and Receive FIFO
The transmit and receive FIFOs may both be accessed via the same 8-bit word in the UART_DR register.
The transmit FIFO stores up to 32 8-bit words and can be written using writes to UART_DR. The receive
FIFO stores up to 32 12-bit words and can be read using reads to UART_DR. Note that each 12-bit receive
FIFO word includes an 8-bit data word and a 4-bit error status word.
17.6 UART Registers
Serial UART
INSTANCE 0 BASE ADDRESS:0x4001C000
INSTANCE 1 BASE ADDRESS:0x4001D000
17.6.1 Register Memory Map
Table 1036: UART Register Map
Address(s) Register Name Description
0x4001C000
0x4001D000
DR UART Data Register
0x4001C004
0x4001D004
RSR UART Status Register
0x4001C018
0x4001D018
FR Flag Register
0x4001C020
0x4001D020
ILPR IrDA Counter
0x4001C024
0x4001D024
IBRD Integer Baud Rate Divisor
0x4001C028
0x4001D028
FBRD Fractional Baud Rate Divisor
0x4001C02C
0x4001D02C
LCRH Line Control High
0x4001C030
0x4001D030
CR Control Register
0x4001C034
0x4001D034
IFLS FIFO Interrupt Level Select
0x4001C038
0x4001D038
IER Interrupt Enable
0x4001C03C
0x4001D03C
IES Interrupt Status
0x4001C040
0x4001D040
MIS Masked Interrupt Status
0x4001C044
0x4001D044
IEC Interrupt Clear