User Manual

Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 706 of 909 2019 Ambiq Micro, Inc.

Table 1035: STAT Register Bits

Bit Name Reset RW Description

31 SBOOT 0x0 RW

Set when booting securely (SBL).

30 FBOOT 0x0 RW

Set if current boot was initiated by soft reset and resulted in Fast Boot

(SBL).

29:11 RSVD 0x0 RW

RESERVED.

10 BOBSTAT 0x0 RW

A BLE/Burst Regulator Brownout Event occurred (SBL).

9BOFSTAT 0x0RW

A Memory Regulator Brownout Event occurred (SBL).

8BOCSTAT 0x0RW

A Core Regulator Brownout Event occurred (SBL).

7BOUSTAT 0x0RW

An Unregulated Supply Brownout Event occurred (SBL).

6 WDRSTAT 0x0 RW

Reset was initiated by a Watchdog Timer Reset (SBL).

5DBGRSTAT 0x0RW

Reset was a initiated by Debugger Reset (SBL).

4POIRSTAT 0x0RW

Reset was a initiated by Software POI Reset (SBL).

3SWRSTAT 0x0RW

Reset was a initiated by SW POR or AIRCR Reset (SBL).

2BORSTAT 0x0RW

Reset was initiated by a Brown-Out Reset (SBL).

1PORSTAT 0x0RW

Reset was initiated by a Power-On Reset (SBL).

0 EXRSTAT 0x0 RW

Reset was initiated by an External Reset (SBL).