User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 705 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
16.8.2.8 INTSET Register
Reset Interrupt register: Set
OFFSET: 0x0000020C
INSTANCE 0 ADDRESS: 0x4000020C
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for
testing purposes).
16.8.2.9 STAT Register
Status Register (SBL)
OFFSET: 0x0FFFF000
INSTANCE 0 ADDRESS: 0x4FFFF000
This register contains the status for brownout events and the causes for resets.in NOTE 1: All bits in this
register, including reserved bits, are writable. Therefore care should be taken not to write this register.\n
NOTE 1: This register does not retain its value across a core deepsleep cycle. Therefore applications
needing to use this value after deep sleep must copy and save this register to SRAM before initiating the
first deep sleep cycle.
Table 1032: INTSET Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
BODH
Table 1033: INTSET Register Bits
Bit Name Reset RW Description
31:1 RSVD 0x0 RO
RESERVED.
0BODH 0x0RW
Enables an interrupt that triggers when VCC is below BODH level.
Table 1034: STAT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
SBOOT
FBOOT
RSVD
BOBSTAT
BOFSTAT
BOCSTAT
BOUSTAT
WDRSTAT
DBGRSTAT
POIRSTAT
SWRSTAT
BORSTAT
PORSTAT
EXRSTAT