User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 704 of 909 2019 Ambiq Micro, Inc.
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INSTANCE 0 ADDRESS: 0x40000204
Read bits from this register to discover the cause of a recent interrupt.
16.8.2.7 INTCLR Register
Reset Interrupt register: Clear
OFFSET: 0x00000208
INSTANCE 0 ADDRESS: 0x40000208
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
Table 1028: INTSTAT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
BODH
Table 1029: INTSTAT Register Bits
Bit Name Reset RW Description
31:1 RSVD 0x0 RO
RESERVED.
0BODH 0x0RW
Enables an interrupt that triggers when VCC is below BODH level.
Table 1030: INTCLR Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
BODH
Table 1031: INTCLR Register Bits
Bit Name Reset RW Description
31:1 RSVD 0x0 RO
RESERVED.
0BODH 0x0RW
Enables an interrupt that triggers when VCC is below BODH level.