User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 703 of 909 2019 Ambiq Micro, Inc.
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16.8.2.5 INTEN Register
Reset Interrupt register: Enable
OFFSET: 0x00000200
INSTANCE 0 ADDRESS: 0x40000200
Set bits in this register to allow this module to generate the corresponding interrupt.
16.8.2.6 INTSTAT Register
Reset Interrupt register: Status
OFFSET: 0x00000204
Table 1024: TPIURST Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
TPIURST
Table 1025: TPIURST Register Bits
Bit Name Reset RW Description
31:1 RSVD 0x0 RW
RESERVED.
0TPIURST 0x0RW
Static reset for the TPIU. Write to '1' to assert reset to TPIU. Write to '0' to
clear the reset.
Table 1026: INTEN Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
BODH
Table 1027: INTEN Register Bits
Bit Name Reset RW Description
31:1 RSVD 0x0 RO
RESERVED.
0BODH 0x0RW
Enables an interrupt that triggers when VCC is below BODH level.