User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 701 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
16.8.2 RSTGEN Registers
16.8.2.1 CFG Register
Configuration Register
OFFSET: 0x00000000
INSTANCE 0 ADDRESS: 0x40000000
Reset configuration register. This controls the reset enables for brownout condition, and for the expiration
of the watch dog timer.
16.8.2.2 SWPOI Register
Software POI Reset
OFFSET: 0x00000004
INSTANCE 0 ADDRESS: 0x40000004
This is the software POI reset. writing the key value to this register will trigger a POI to the system. This
will cause a reset to all blocks except for registers in clock gen, RTC and the stimer.
Table 1018: CFG Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
WDREN
BODHREN
Table 1019: CFG Register Bits
Bit Name Reset RW Description
31:2 RSVD 0x0 RO
RESERVED.
1 WDREN 0x0 RW
Watchdog Timer Reset Enable. NOTE: The WDT module must also be con-
figured for WDT reset. This includes enabling the RESEN bit in WDTCFG
register in Watch dog timer block.
0BODHREN 0x0RW
Brown out high (2.1v) reset enable.
Table 1020: SWPOI Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD SWPOIKEY