User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 700 of 909 2019 Ambiq Micro, Inc.
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16.5 Software Reset
A reset may be generated via software using the Application Interrupt and Reset Control Register (AIRCR)
defined in the Cortex-M4. For additional information on the AIRCR, see the ARM document titled “Cortex-
M4 Devices Generic User Guide.” The software reset request is not maskable.A second source for the
identical software reset functionality is made available through the SWPOR register in the RSTGEN
peripheral module.
16.6 Software Power On Initialization
The SWPOI register enables the capability for software to perform a substantial reset that includes
reloading the low power analog circuitry trim settings set in the flash information space. These values are
not re-loaded from flash info space for Software Reset or External Reset events.
16.7 Watchdog Expiration
The Watchdog Timer sub-module generates an interrupt if it has not been properly managed by software
within a pre-defined time. The watchdog reset is maskable.
16.8 RSTGEN Registers
MCU Reset Generator
INSTANCE 0 BASE ADDRESS:0x40000000
16.8.1 Register Memory Map
Table 1017: RSTGEN Register Map
Address(s) Register Name Description
0x40000000 CFG Configuration Register
0x40000004 SWPOI Software POI Reset
0x40000008 SWPOR Software POR Reset
0x40000014 TPIURST TPIU reset
0x40000200 INTEN Reset Interrupt register: Enable
0x40000204 INTSTAT Reset Interrupt register: Status
0x40000208 INTCLR Reset Interrupt register: Clear
0x4000020C INTSET Reset Interrupt register: Set
0x4FFFF000 STAT Status Register (SBL)