User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 696 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
15.2.2.7 INTCLR Register
WDT Interrupt register: Clear
OFFSET: 0x00000208
INSTANCE 0 ADDRESS: 0x40024208
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
15.2.2.8 INTSET Register
WDT Interrupt register: Set
OFFSET: 0x0000020C
INSTANCE 0 ADDRESS: 0x4002420C
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for
testing purposes).
Table 1013: INTCLR Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
WDTIN
Table 1014: INTCLR Register Bits
Bit Name Reset RW Description
31:1 RSVD 0x0 RO
This bitfield is reserved for future use.
0WDTINT 0x0RW
Watchdog Timer Interrupt.
Table 1015: INTSET Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
WDTIN