User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 695 of 909 2019 Ambiq Micro, Inc.
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INSTANCE 0 ADDRESS: 0x40024200
Set bits in this register to allow this module to generate the corresponding interrupt.
15.2.2.6 INTSTAT Register
WDT Interrupt register: Status
OFFSET: 0x00000204
INSTANCE 0 ADDRESS: 0x40024204
Read bits from this register to discover the cause of a recent interrupt.
Table 1009: INTEN Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
WDTIN
Table 1010: INTEN Register Bits
Bit Name Reset RW Description
31:1 RSVD 0x0 RO
This bitfield is reserved for future use.
0WDTINT 0x0RW
Watchdog Timer Interrupt.
Table 1011: INTSTAT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
WDTIN
Table 1012: INTSTAT Register Bits
Bit Name Reset RW Description
31:1 RSVD 0x0 RO
This bitfield is reserved for future use.
0WDTINT 0x0RW
Watchdog Timer Interrupt.