User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 694 of 909 2019 Ambiq Micro, Inc.
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15.2.2.4 COUNT Register
Current Counter Value for WDT
OFFSET: 0x0000000C
INSTANCE 0 ADDRESS: 0x4002400C
This register holds the current count for the watch dog timer. This is a read only register. SW cannot set
the value in the counter, but can reset it.
15.2.2.5 INTEN Register
WDT Interrupt register: Enable
OFFSET: 0x00000200
Table 1005: LOCK Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD LOCK
Table 1006: LOCK Register Bits
Bit Name Reset RW Description
31:8 RSVD 0x0 RO
This bitfield is reserved for future use.
7:0 LOCK 0x0 WO
Writing 0x3A locks the watchdog timer. Once locked, the WDTCFG reg can-
not be written and WDTEN is set.
KEYVALUE = 0x3A - This is the key value to write to WDTLOCK to lock the
WDT.
Table 1007: COUNT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD COUNT
Table 1008: COUNT Register Bits
Bit Name Reset RW Description
31:8 RSVD 0x0 RO
This bitfield is reserved for future use.
7:0 COUNT 0x0 RO
Read-Only current value of the WDT counter