User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 693 of 909 2019 Ambiq Micro, Inc.
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15.2.2.2 RSTRT Register
Restart the watchdog timer.
OFFSET: 0x00000004
INSTANCE 0 ADDRESS: 0x40024004
This register will Restart the watchdog timer. Writing a special key value into this register will result in the
watch dog timer being reset, so that the count will start again. It is expected that the software will
periodically write to this register to indicate that the system is functional. The watch dog timer can continue
running when the system is in deep sleep, and the interrupt will trigger the wake. After the wake, the core
can reset the watch dog timer.
15.2.2.3 LOCK Register
Locks the WDT
OFFSET: 0x00000008
INSTANCE 0 ADDRESS: 0x40024008
This register locks the watch dog timer. Once it is locked, the configuration register (WDTCFG) for watch
dog timer cannot be written to.
0WDTEN 0x0RW
This bitfield enables the WDT.
Table 1003: RSTRT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD RSTRT
Table 1004: RSTRT Register Bits
Bit Name Reset RW Description
31:8 RSVD 0x0 RO
This bitfield is reserved for future use.
7:0 RSTRT 0x0 WO
Writing 0xB2 to WDTRSTRT restarts the watchdog timer. This is a write
only register. Reading this register will only provide all 0.
KEYVALUE = 0xB2 - This is the key value to write to WDTRSTRT to restart
the WDT. This is a write only register.
Table 1002: CFG Register Bits
Bit Name Reset RW Description