User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 684 of 909 2019 Ambiq Micro, Inc.
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14.2.2.20STMINTEN Register
STIMER Interrupt registers: Enable
OFFSET: 0x00000300
INSTANCE 0 ADDRESS: 0x40008300
Set bits in this register to allow this module to generate the corresponding interrupt.
Table 991: SNVR3 Register Bits
Bit Name Reset RW Description
31:0 SNVR3 0x0 RW
Value of the 32-bit counter as it ticks over.
Table 992: STMINTEN Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
CAPTURED CAPTUREC
CAPTUREB CAPTUREA
OVERFLOW
COMPAREH
COMPAREG
COMPAREF
COMPAREE
COMPARED COMPAREC
COMPAREB COMPAREA
Table 993: STMINTEN Register Bits
Bit Name Reset RW Description
31:13 RSVD 0x0 RO
RESERVED.
12 CAPTURED 0x0 RW
CAPTURE register D has grabbed the value in the counter
CAPD_INT = 0x1 - Capture D interrupt status bit was set.
11 CAPTUREC 0x0 RW
CAPTURE register C has grabbed the value in the counter
CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set.
10 CAPTUREB 0x0 RW
CAPTURE register B has grabbed the value in the counter
CAPB_INT = 0x1 - CAPTURE B interrupt status bit was set.
9 CAPTUREA 0x0 RW
CAPTURE register A has grabbed the value in the counter
CAPA_INT = 0x1 - CAPTURE A interrupt status bit was set.
8 OVERFLOW 0x0 RW
COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.
OFLOW_INT = 0x1 - Overflow interrupt status bit was set.
7COMPAREH 0x0RW
COUNTER is greater than or equal to COMPARE register H.
COMPARED = 0x1 - COUNTER greater than or equal to COMPARE regis-
ter.