User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 682 of 909 2019 Ambiq Micro, Inc.
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14.2.2.16SNVR0 Register
System Timer NVRAM_A Register
OFFSET: 0x000001F0
INSTANCE 0 ADDRESS: 0x400081F0
The NVRAM_A Register contains a portion of the stored epoch offset associated with the time in the
COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to
survive all reset level except POI and full power cycles.
14.2.2.17SNVR1 Register
System Timer NVRAM_B Register
OFFSET: 0x000001F4
INSTANCE 0 ADDRESS: 0x400081F4
The NVRAM_B Register contains a portion of the stored epoch offset associated with the time in the
COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to
survive all reset level except POI and full power cycles.
Table 983: SCAPT3 Register Bits
Bit Name Reset RW Description
31:0 SCAPT3 0x0 RO
Whenever the event is detected, the value in the COUNTER is copied into
this register and the corresponding interrupt status bit is set.
Table 984: SNVR0 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
SNVR0
Table 985: SNVR0 Register Bits
Bit Name Reset RW Description
31:0 SNVR0 0x0 RW
Value of the 32-bit counter as it ticks over.
Table 986: SNVR1 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
SNVR1