User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 676 of 909 2019 Ambiq Micro, Inc.
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14.2.2.5 SCMPR1 Register
Compare Register B
OFFSET: 0x00000154
INSTANCE 0 ADDRESS: 0x40008154
The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match
criterion in the configuration register is met then a corresponding interrupt status bit is set. The match
criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE
register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware
does the addition to the COUNTER value in the STIMER clock domain so that the math is precise.
Reading this register shows the COUNTER value at which this interrupt will occur.
14.2.2.6 SCMPR2 Register
Compare Register C
OFFSET: 0x00000158
INSTANCE 0 ADDRESS: 0x40008158
The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match
criterion in the configuration register is met then a corresponding interrupt status bit is set. The match
criterion is defined as COUNTER equal to COMPARE. To establish a desired value in this COMPARE
register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware
does the addition to the COUNTER value in the STIMER clock domain so that the math is precise.
Reading this register shows the COUNTER value at which this interrupt will occur.
Table 962: SCMPR1 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
SCMPR1
Table 963: SCMPR1 Register Bits
Bit Name Reset RW Description
31:0 SCMPR1 0x0 RW
Compare this value to the value in the COUNTER register according to the
match criterion, as selected in the COMPARE_B_EN bit in the REG_CTIM-
ER_STCGF register.
Table 964: SCMPR2 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
SCMPR2