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Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 673 of 909 2019 Ambiq Micro, Inc.
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13
COM-
PARE_F_EN
0x0 RW
Selects whether compare is enabled for the corresponding SCMPR register.
If compare is enabled, the interrupt status is set once the comparision is
met.
DISABLE = 0x0 - Compare F disabled.
ENABLE = 0x1 - Compare F enabled.
12
COM-
PARE_E_EN
0x0 RW
Selects whether compare is enabled for the corresponding SCMPR register.
If compare is enabled, the interrupt status is set once the comparision is
met.
DISABLE = 0x0 - Compare E disabled.
ENABLE = 0x1 - Compare E enabled.
11
COM-
PARE_D_EN
0x0 RW
Selects whether compare is enabled for the corresponding SCMPR register.
If compare is enabled, the interrupt status is set once the comparision is
met.
DISABLE = 0x0 - Compare D disabled.
ENABLE = 0x1 - Compare D enabled.
10
COM-
PARE_C_EN
0x0 RW
Selects whether compare is enabled for the corresponding SCMPR register.
If compare is enabled, the interrupt status is set once the comparision is
met.
DISABLE = 0x0 - Compare C disabled.
ENABLE = 0x1 - Compare C enabled.
9
COM-
PARE_B_EN
0x0 RW
Selects whether compare is enabled for the corresponding SCMPR register.
If compare is enabled, the interrupt status is set once the comparision is
met.
DISABLE = 0x0 - Compare B disabled.
ENABLE = 0x1 - Compare B enabled.
8
COM-
PARE_A_EN
0x0 RW
Selects whether compare is enabled for the corresponding SCMPR register.
If compare is enabled, the interrupt status is set once the comparision is
met.
DISABLE = 0x0 - Compare A disabled.
ENABLE = 0x1 - Compare A enabled.
7:4 RSVD 0x0 RO
RESERVED.
3:0 CLKSEL 0x0 RW
Selects an appropriate clock source and divider to use for the System Timer
clock.
NOCLK = 0x0 - No clock enabled.
HFRC_DIV16 = 0x1 - 3MHz from the HFRC clock divider.
HFRC_DIV256 = 0x2 - 187.5KHz from the HFRC clock divider.
XTAL_DIV1 = 0x3 - 32768Hz from the crystal oscillator.
XTAL_DIV2 = 0x4 - 16384Hz from the crystal oscillator.
XTAL_DIV32 = 0x5 - 1024Hz from the crystal oscillator.
LFRC_DIV1 = 0x6 - Approximately 1KHz from the LFRC oscillator (uncali-
brated).
CTIMER0A = 0x7 - Use CTIMER 0 section A as a prescaler for the clock
source.
CTIMER0B = 0x8 - Use CTIMER 0 section B (or A and B linked together) as
a prescaler for the clock source.
Table 955: STCFG Register Bits
Bit Name Reset RW Description