User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 672 of 909 2019 Ambiq Micro, Inc.
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14.2.2 STIMER Registers
14.2.2.1 STCFG Register
Configuration Register
OFFSET: 0x00000140
INSTANCE 0 ADDRESS: 0x40008140
The STIMER Configuration Register contains the software control for selecting the clock divider and
source feeding the system timer.
Table 954: STCFG Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
FREEZE
CLEAR
RSVD
COMPARE_H_EN
COMPARE_G_EN
COMPARE_F_EN
COMPARE_E_EN
COMPARE_D_EN COMPARE_C_EN
COMPARE_B_EN COMPARE_A_EN
RSVD CLKSEL
Table 955: STCFG Register Bits
Bit Name Reset RW Description
31 FREEZE 0x1 RW
Set this bit to one to freeze the clock input to the COUNTER register. Once
frozen, the value can be safely written from the MCU. Unfreeze to resume.
THAW = 0x0 - Let the COUNTER register run on its input clock.
FREEZE = 0x1 - Stop the COUNTER register for loading.
30 CLEAR 0x0 RW
Set this bit to one to clear the System Timer register. If this bit is set to '1',
the system timer register will stay cleared. It needs to be set to '0' for the
system timer to start running.
RUN = 0x0 - Let the COUNTER register run on its input clock.
CLEAR = 0x1 - Stop the COUNTER register for loading.
29:16 RSVD 0x0 RO
RESERVED.
15
COM-
PARE_H_EN
0x0 RW
Selects whether compare is enabled for the corresponding SCMPR register.
If compare is enabled, the interrupt status is set once the comparision is
met.
DISABLE = 0x0 - Compare H disabled.
ENABLE = 0x1 - Compare H enabled.
14
COM-
PARE_G_EN
0x0 RW
Selects whether compare is enabled for the corresponding SCMPR register.
If compare is enabled, the interrupt status is set once the comparision is
met.
DISABLE = 0x0 - Compare G disabled.
ENABLE = 0x1 - Compare G enabled.