User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 651 of 909 2019 Ambiq Micro, Inc.
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13.21.2.58OUTCFG0 Register
Counter/Timer Output Config 0
OFFSET: 0x00000104
INSTANCE 0 ADDRESS: 0x40008104
Pad output configuration 0.
6ENA3 0x1RW
Alternate enable for A3
LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
5ENB2 0x1RW
Alternate enable for B2
LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
4ENA2 0x1RW
Alternate enable for A2
LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
3ENB1 0x1RW
Alternate enable for B1
LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
2ENA1 0x1RW
Alternate enable for A1
LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
1ENB0 0x1RW
Alternate enable for B0
LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
0ENA0 0x1RW
Alternate enable for A0
LCO = 0x1 - Use local enable.
DIS = 0x0 - Disable CTIMER.
Table 935: OUTCFG0 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
CFG9 CFG8 CFG7 CFG6 CFG5
RSVD
CFG4 CFG3 CFG2 CFG1 CFG0
Table 934: GLOBEN Register Bits
Bit Name Reset RW Description