User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 647 of 909 2019 Ambiq Micro, Inc.
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13.21.2.55CMPRAUXB7 Register
Counter/Timer B7 Compare Registers
OFFSET: 0x000000F8
INSTANCE 0 ADDRESS: 0x400080F8
Enhanced compare limits for timer half B.
13.21.2.56AUX7 Register
Counter/Timer Auxiliary
OFFSET: 0x000000FC
INSTANCE 0 ADDRESS: 0x400080FC
Control bit fields for both halves of timer 0.
Table 928: CMPRAUXA7 Register Bits
Bit Name Reset RW Description
31:16 CMPR3A7 0x0 RW
Counter/Timer A7 Compare Register 3. Holds the upper limit for timer half
A.
15:0 CMPR2A7 0x0 RW
Counter/Timer A7 Compare Register 2. Holds the lower limit for timer half A.
Table 929: CMPRAUXB7 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR3B7 CMPR2B7
Table 930: CMPRAUXB7 Register Bits
Bit Name Reset RW Description
31:16 CMPR3B7 0x0 RW
Counter/Timer B7 Compare Register 3. Holds the upper limit for timer half
B.
15:0 CMPR2B7 0x0 RW
Counter/Timer B7 Compare Register 2. Holds the lower limit for timer half B.